Latches & Flip-Flops: SR Latch with an Invalid Flag, D, JK and T Flip-Flops on Rising Clock Edges
This lesson is part of the course
In this lesson
You step an SR latch and D, JK and T flip-flops through 12 steps: each new state comes from the row above, the flip-flops change only on rising clock edges, and a timing chart shows how D is sampled.
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Lessons in this course
- Gates as Formulas: AND, OR, NOT, NAND, NOR, XOR & an XOR Built Only from NANDs Locked
- From Truth Table to Expression: Minterms, Sum of Products & a Check Column Locked
- Karnaugh Maps: Gray-Code Layout, Groups of 1, 2, 4 & 8, Don't-Care Cells and the Literals You Save Locked
- Binary Adders: Bits with MOD and INT, Half & Full Adders, a 4-Bit Ripple-Carry Adder and the Overflow Flag Locked
- Multiplexers & Decoders: Select Bits, One-Hot Lines, a Display Decoder from a Lookup Table and a Parity Bit Locked
- Latches & Flip-Flops: SR Latch with an Invalid Flag, D, JK and T Flip-Flops on Rising Clock Edges Locked
- Counters & Shift Registers: a 3-Bit Synchronous Counter, a Mod-6 Counter with Reset and a Pattern Detector Locked
- Capstone – A Traffic-Light State Machine: State Table, Combined Keys, 24 Clock Ticks and the Fastest Clock Locked