Address Bits: Offset, Index and Tag from Cache Size, Block Size and Ways
This lesson is part of the course
In this lesson
You derive the number of sets and the offset, index and tag bits of a small direct-mapped cache, then split six addresses into block number, set index and tag.
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Lessons in this course
- The Memory Hierarchy: Sizes, Latencies, Cycles to Time and Why Locality Matters Locked
- Address Bits: Offset, Index and Tag from Cache Size, Block Size and Ways Locked
- A Direct-Mapped Cache on a Trace: Last Use of a Set, Stored Tag, Hit or Miss Locked
- Hit Rate and Miss Types: Compulsory vs Conflict Misses and the Best You Could Reach Locked
- 2-Way Set-Associative with LRU: Two Ways per Set, Last-Use Times and the Victim Locked
- Average Memory Access Time: Hit Time, Miss Rate, Miss Penalty and a Second Level Locked
- Write Policies: Write-Through vs Write-Back Traffic, Dirty Blocks and the Final Flush Locked
- Comparing Cache Designs: Size × Block Size, Miss Penalty, AMAT per Design and a Chart Locked