Tutorvo

Hit Rate and Miss Types: Compulsory vs Conflict Misses and the Best You Could Reach

Lesson 4 of 815 minLab

This lesson is part of the course

In this lesson

You take the simulator's results for the trace of the last lesson, count how often each block was used before, label every miss as compulsory or conflict and calculate the hit rate a cache without conflicts could reach.

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Lessons in this course

  1. The Memory Hierarchy: Sizes, Latencies, Cycles to Time and Why Locality MattersLab15 min Locked
  2. Address Bits: Offset, Index and Tag from Cache Size, Block Size and WaysLab15 min Locked
  3. A Direct-Mapped Cache on a Trace: Last Use of a Set, Stored Tag, Hit or MissLab15 min Locked
  4. Hit Rate and Miss Types: Compulsory vs Conflict Misses and the Best You Could ReachLab15 min Locked
  5. 2-Way Set-Associative with LRU: Two Ways per Set, Last-Use Times and the VictimLab15 min Locked
  6. Average Memory Access Time: Hit Time, Miss Rate, Miss Penalty and a Second LevelLab15 min Locked
  7. Write Policies: Write-Through vs Write-Back Traffic, Dirty Blocks and the Final FlushLab15 min Locked
  8. Comparing Cache Designs: Size × Block Size, Miss Penalty, AMAT per Design and a ChartLab15 min Locked