CPU Caches by Hand: Address Bits, Direct-Mapped & Set-Associative Caches, Hit/Miss Traces, Average Memory Access Time & Multi-Level Caches

What you'll build

What you will be able to do

Each lab ends with a concrete result that you build yourself and the checker confirms, cell by cell.

• Compare the levels of a fictional memory hierarchy by size and latency, turn cycles into time for a loop of 10,000 reads and see why reading an array in order needs so few trips to memory.
• Derive the number of sets and the offset, index and tag bits of a small direct-mapped cache, then split six addresses into block number, set index and tag.
• Run a 12-access trace through a tiny direct-mapped cache: for every access you find the last earlier access to the same set, read which tag that left in the line, decide hit or miss and calculate the hit rate.
• Take the simulator's results for the trace of the last lesson, count how often each block was used before, label every miss as compulsory or conflict and calculate the hit rate a cache without conflicts could reach.
• Run the same trace through a 2-way set-associative cache of the same total size: decide hit or miss against both ways of the set, pick the least recently used way as the victim and measure how many misses the extra way avoids.
• Calculate the average memory access time of the simulator's processor with one and with two cache levels, the global miss rate and how sensitive the result is to the L1 miss rate.
• Count the bytes that travel to memory on a short read/write trace under write-through and under write-back, including dirty evictions and the final flush, and see which policy saves traffic.
• Compare eight cache designs from the simulator: work out the miss penalty from the block size, the AMAT of every design, pick the best one and show all eight in a column chart.